Our VLSI Physical Design & Verification course offers you the opportunity to gain hands-on experience on the various implementation and sign-off steps (from RTL to GDS-II) in back-end flow, such as Physical Synthesis, Floor-Planning, Placement, Clock Tree Synthesis, Routing, and Static Timing Analysis, LVS and DRC with the help of industry-standard EDA tools, which makes you industry-ready.

               This process produces a set of layout files, which describe the position of cells, and routes for the interconnections between them. The layout is subject to constraints like area, power, and performance. Physical design of ASICs is the process of transforming the circuit description into the physical layout.