STA & Synthesis – Blrchipz

STA | Synth | LEC | CLP |PDN

This is integrated course of VLSI which covers most important part of semiconductor industry . This course will cover Synthesis , Timing and Power analysis of the Chip . This course is also included with FV/LEC using conformal & formality. EM/IR also will be covered under this course .

EDA Tools used for this course :-

Timing: Primetime
Synth: Genus/DC
LEC: Formality
Power : Redhawk

key features

Synthesis

Setting up the Synthesis Flow
Developing Constraints
Logic and Physical Aware Synthesis Using Industry Standard Tools

STA

Setting up the STA flow
Develop Timing Constraints for Multiple Modes
Timing Analysis for Multi Modes & Multi Corners
Timing ECOs using TSO or DMSA
SI Analysis

Mode of the training : Online | Offline classroom | 1:1| Weekend
Projects: 2 months
Theory and labs : 6 Months
Internship: 6 months
Support with resume update
Mock interviews
100 % placement assistance

LEC | CLP

Setting up the LEC and CLP flow
Block Level and Top Level LEC and CLP Runs
Analysis & Debug skills for Complex Issues
EM/IR

Have any Questions? Contact: +918788083776 | mail : [email protected]